7段数码管显现驱动vhdl程序

再修改一个7段数码管(共阴极)显现驱动程序：
Library ieee;
Use ieee.std_logic_1164.all;
Entity QDLED7 is
PORT(DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a,b,c,d,e,f,g:out std_logic);
end QDLED7;
Architecture LED of QDLED7 is
signal y: STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
process(DATA)
begin
case DATA is
when “0000”=>y<="1111110" ;
when “0001”=>y<="0110000" ;
when “0010”=>y<="1101101" ;
when “0011”=>y<="1111001" ;
when “0100”=>y<="0110011" ;
when “0101”=>y<="1011011" ;
when “0110”=>y<="1011111" ;
when “0111”=>y<="1110000" ;
when “1000”=>y<="1111111" ;
when “1001”=>y<="1111011" ;
when others=>null;
end case;
a<=y(6);b<=y(5);c<=y(4);
d<=y(3);e<=y(2);f<=y(1);g<=y(0);
end process;
end;