1：UCS（Unified Clock System）包括5个时钟源：
XT1CLK：能够用于低频率的32.768KHZ或许4~32MHZ的频率。但不是每一个设备都支撑高频率的，有些只支撑32.768KHZ。
VLOCLK：内部低功耗，低频率的时钟，典型值为10KHZ。
REFOCLK：内部时钟，典型值32.768KHZ。
DCOCLK: Internal digitally-controlled oscillator (DCO) that can be stabilized by the FLL。
XT2CLK：高频时钟源，外部时钟，4 MHz到32 MHz。
2：咱们可用的从UCS模块出来的3个时钟：
ACLK:辅佐时钟。
MCLK：主时钟。
;SMCLK：体系子时钟。
3：时钟操作:
After a PUC, the UCS module default configuration is:
1） XT1 in LF mode is selected as the oscillator source for XT1CLK. XT1CLK is selected for ACLK.
2） DCOCLKDIV is selected for MCLK.
3） DCOCLKDIV is selected for SMCLK.
4） FLL operation is enabled and XT1CLK is selected as the FLL reference clock, FLLREFCLK.
5 ）XIN and XOUT pins are set to general-purpose I/Os and XT1 remains disabled until the I/O ports are
configured for XT1 operation.
6 ）When available, XT2IN and XT2OUT pins are set to general-purpose I/Os and XT2 is disabled.
4：设置时钟的相关寄存器：
UCSCTL0~UCSCTL8。
