Luke Miller并非一开始便是HLS（高层次归纳）的倡导者。在运用前期的东西版别的时分，他好像有过一些糟糕的阅历。他写道： “……我的心筑起心墙，我需求协助。”走运的是，现在的他好像现现已过了一个12步HLS培训活动， 现在能够运用Xilinx Vivado HLS有效地开展工作了。
SemiWiki 有了一位新的博主，被称为“The FPGA Expert（FPGA专家）”。经过LinkedIn简略查找，我得知这位FPGA专家是Luke Miller，他最近宣布了一篇博文，介绍怎么运用高层次归纳（HLS）开发从C到其他HLL版别的各种加快硬件。 尽管不像“手把手的菜谱”那样详细翔实，但仍然十分风趣。
Miller曾经在IBM公司担任过ASIC规划师，在Lockheed担任过硬件师（工程师/架构师），现在是一位具有军事和航空规划阅历的PE。Miller的网站名为FPGA Expert，上面有一段特别的叙述其个人阅历的视频，其间描绘了多项军事、航空和医疗项目（飞机、雷达和医疗成像），所以，我猜他应该具有十分丰富的FPGA规划阅历。他的网站证明了这个猜测。 Miller好像也十分了解HLS。他写道：
“规划时刻的加快并非从C到VHDL的转化， 真实起到关键因素的是仿真域 —您再也无需经过RTL逐件验证每项规划。”
Luke Miller并非一向都是HLS（高层次归纳）的倡导者。在运用前期的东西版别的时分，他好像有些糟糕的阅历。。他写道：“……我的心筑起心墙，我需求协助。”走运的是，他好像现现已过了一个12步HLS培训活动， 现在能够经过Xilinx Vivado HLS有效地开展工作了。
点击此处，阅览Miller有关HLS的主张：“高层次归纳 —它真的行！ （ High Level Synthesis – It’s for Real） ”%96-%92s-real.html
下面是Miller的全文供参阅：
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High Level Synthesis – It’s for Real
by
theFPGAexpert
Published on 04-11-2013 06:30 PM
It was spring 2010 and I was asked to attend an HLS (High Level Synthesis) meeTIng. To be honest I cringed, after my bad relaTIonship with Accel DSP and broken promises my heart was all walled up and needed counseling. But my management had a way of making me an offer I could not refuse, like keeping my job. So reluctantly I went. Does your employer do lunch and learns instead of real training? You know what that equals right? A 1/8 pay cut, but let’s play nice.
Anyways after the usual introducTIons at the meeTIng they began to get into the meat of the tool. I quickly diverted and asked if we could see the tool in action and move away from the power point and boy did they. First up was a cookie cutter FIR filter but it worked, really! Then they moved into floating point designs etc. This HLS was the greatest thing since sliced bread. I saw its potential and I needed to try it. We all agreed on an evaluation period. Now I am by no means the best coder in the world, but even the best would have a hard time beating the HLS tool with respect to design time, area and latency.
What HLS is not: It is not a coder in a box, thus sit down the software guy and have him designing FPGAs. You need to understand the FPGA, no exceptions or you will have a fat, slow design. The C or its variant will need to be restructured, smartly, thus helping the tool out so it can perform better. It is not a button you press and you have a bit image. I know how program managers think.
I leverage HLS tools in this fashion. I view it as Xilinx Corgen on steroids which are driven by a C file. The speed up in design time is not in the translation from C to VHDL but really is in the simulation domain. You are no longer verifying designs piece by piece using RTL. For example, I design a Beamfomer in C. I compile it and then run ‘a.exe’ and verify that the answer matches the expects. That took about a second. For many PRIs of data that could of taken hours in ModelSim. Catching on? I then bring up the HLS tool and pull in the C file and the tool reports the latency, area, clock frequency etc. From that information I can determine which FPGA to use. I then start using directives to optimize the area / latency by using unrolls and pipeline directives. About an hour later my beamformer is done. I then simulate the RTL at my top level but I already know the math works and the tool took care of the boundary conditions. The goal of this article is by no means a recipe on HLS usage but hopefully entices you to check it out, you won’t be sorry.
